DELAYS

Net Delay

module netdelay(x,y);

input x; 

output y; 

wire #2 nn; 

not (nn,x); 

buf y = x;  

endmodule

module tst_netdelay ;

reg x; 

wire y; 

netdelay nd(x,y); 

initial

begin

 x =1'b0; 

#6 x =~x; 

end

initial #20 $stop; 

endmodule

module to demonstrate different delays for rise and fall times on a net.

module netdelay1(x,y); 

input x; 

output y; 

wire #(2,1) nn; 

not (nn,x); 

y=nn;

endmodule

module tst_netdelay1; //test-bench 

reg x; 

wire y; 

netdelay1 nd(x,y); 

initial

begin

 x =1'b0; 

#6 x =~x; 

end

initial #20 $stop; 

endmodule

Gate Delay

module gade(a,a1,b,c,b1,c1);

input b,c,b1,c1; 

output a,a1; 

or #3gg1(a1,c1,b1); 

and #(2,1)gg2(a,c,b); 

endmodule

module tst_gade();//test-bench 

reg b,c,b1,c1; 

wire c,c1; 

gade ggde(a,a1,b,c,b1,c1); 

initial

begin

b =1'b0;c =1'b0;b1 =1'b0;c1=1'b0; 

end

always

begin

#5 b =1'b0;c =1'b0;b1 =1'b1;c1=1'b1; 

#5 b =1'b1;c =1'b1;b1 =1'b0;c1=1'b0; 

#5 b =1'b1;c =1'b0;b1 =1'b1;c1=1'b0; 

#5 b =1'b0;c =1'b1;b1 =1'b0;c1=1'b1; 

#5 b =1'b1;c =1'b1;b1 =1'b1;c1=1'b1; 

#5 b =1'b1;c =1'b1;b1 =1'b1;c1=1'b1; 

end

initial $monitor($time , " b= %b , c = %b , b1 = %b ,c1 = %b , a = %b ,a1 = %b" ,b,c,b1,c1,a,a1); 

initial #30 $stop; 

endmodule

Flip-Flop's

An RS Flip-Flop

module srff(s,r,q,qb); 

input s,r; 

output q,qb; 

wire ss,rr; 

not(ss,s),(rr,r);

nand(q,ss,qb);

nand(qb,rr,q);

endmodule

module tstsrff; //test-bench 

reg s,r; 

wire q,qb; 

srff ff(s,r,q,qb); 

initial

begin

s =1'b1; 

r =1'b0; 

end

always

begin

#2 s =1'b0;r =1'b0; 

#2 s =1'b0;r =1'b1; 

#2 s =1'b0;r =1'b0; 

#2 s =1'b1;r =1'b0; 

#2 s =1'b0;r =1'b0; 

end

initial $monitor($time, " s = %b, r = %b, q = %b, qb = %b ",s,r,q,qb); 

initial #20 $stop; 

endmodule

Clocked RS Flip-Flop

module srffcplev(cp,s,r,q,qb);

input cp,s,r; 

output q,qb; 

wire ss,rr; 

nand(ss,s,cp),(rr,r,cp),(q,ss,qb),(qb,rr,q);

endmodule

module srffcplev_tst;// test-bench 

reg cp,s,r; 

wire q,qb; 

srffcplev ff(cp,s,r,q,qb); 

initial

begin

cp=1'b0;

s =1'b1; 

r =1'b0; 

end

always #2cp=~cp; 

always

begin

#4 s =1'b0;r =1'b0; 

#4 s =1'b0;r =1'b1; 

#4 s =1'b0;r =1'b0; 

#4 s =1'b1;r =1'b0; 

#4 s =1'b0;r =1'b0; 

end

initial $monitor($time,"cp = %b ,s = %b , r = %b , q = %b , qb = %b " ,cp,s,r,q,qb); 

initial #20 $stop; 

endmodule

D-Latch

module dlatch(en,d,q,qb); 

input d,en; 

output q,qb; 

wire dd; 

wire s,r; 

not n1(dd,d); 

nand (sb,d,en); 

nand g2(rb,dd,en);

sbrbff ff(sb,rb,q,qb);//Instantiation of the sbrbff

endmodule

module tstdlatch; //test-bench 

reg d,en; 

wire q,qb; 

dlatch ff(en,d,q,qb); 

initial

begin

d = 1'b0; 

en = 1'b0; 

end

always #4 en =~en; 

always #8 d=~d; 

initial $monitor($time," en = %b , d = %b , q = %b , qb= %b " , en,d,q,qb); 

initial #40 $stop; 

endmodule

MUX's

4-to-1 mux

module mux4_1(y,i,s);

input [3:0] i;

input [1:0] s;

output y;

wire [1:0] ss;

wire [3:0]yy;

not (ss[0],s[0]),(ss[1],s[1]);

and (yy[0],i[0],ss[0],ss[1]);

and (yy[1],i[1],s[0],ss[1]);

and (yy[2],i[2],ss[0],s[1]);

and (yy[3],i[3],s[0],s[1]);

or (y,yy[3],yy[2],yy[1],yy[0]);

endmodule

//test-bench

module tst_mux4_1();

reg [3:0]i;

reg [1:0] s;

mux4_1 mm(y,i,s);

initial

begin

#2{i,s} = 6'b 0000_00;

#2{i,s} = 6'b 0001_00;

#2{i,s} = 6'b 0010_01;

#2{i,s} = 6'b 0100_10;

#2{i,s} = 6'b 1000_11;

#2{i,s} = 6'b 0001_00;

end

initial

$monitor($time," input s = %b,y = %b" ,s,y);

endmodule

4-to-1 mux module with tri-state

module trimux4_1(o,e,i,s);

input e;

input [1:0]s;

input [3:0]i;

output o;

tri o;

wire y,y1,y2,y3,y4;

wire [1:0]ss;

not(ss[0],s[0]),(ss[1],s[1]);

and g1(y1,ss[0],ss[1],i[0]);

and g2(y2,ss[1],s[0],i[1]);

and g3(y3,ss[0],s[1],i[2]);

and g4(y4,s[1],s[0],i[3]);

or(y,y3,y2,y1,y2);

bufif1 buf2(o,y,e);

endmodule

//TESTBENCH

module tst_trimux4_1();

reg [1:0]s;

reg [3:0]i;

reg e;

wire o;

trimux4_1 tmx4_1(o,e,i,s);

initial

begin

e =0;i =2'b00;

end

always

begin

#6 e=0;s=2'b00;i=4'b0001;

#6 e=1;s=2'b01;i=4'b0010;
#6 e=1;s=2'b10;i=4'b0100;

#6 e=1;s=2'b10;i=4'b1000;

end

initial $monitor($time ," input e = %b , s= %b , i = %b

, output o = %b " ,e,s,i,o);

initial #48 $stop;

endmodule

2-to-1 mux module formed with tri-state
buffers.

module ttrimux2_1(out,e,i,s);

input[1:0]i;

input e;

input s;

output out;

wire o;

bufif0 g1(o,i[0],s);

bufif1 g2(o,i[1],s);

bufif1 g3(out,o,e);

endmodule

//testbench

module ttst_ttrimux2_1();

reg e;

reg [1:0]i;

reg s;

ttrimux2_1 mm(out,e,i,s);

initial

begin

e =0; i = 2'b 00;end

always

begin

#4 e =0;{i,s} = 3'b 01_0;

#4 e =1;{i,s} = 3'b 01_0;

#4 e =1;{i,s} = 3'b 10_1;

#4 e =1;{i,s} = 3'b 00_1;

#4 e =1;{i,s} = 3'b 10_1;

#4 e =1;{i,s} = 3'b 01_0;

#4 e =1;{i,s} = 3'b 00_0;

#4 e =1;{i,s} = 3'b 11_0;

end

initial $monitor($time ," enable e = %b ,

s= %b , input i = %b ,output out = %b ",e ,s,i,out);

initial #48 $stop;

endmodule

Adder programs

HALF ADDER

module ha(s,ca,a,b);

input a,b;

output s,ca;

xor(s,a,b);

and(ca,a,b);

endmodule

//test-bench

module tstha();

reg a,b;

wire s,ca;

ha hh(s,ca,a,b);

initial

begin

a=0;b=0;

end

always

begin

#2 a=1;b=0;

#2 a=0;b=1;

#2 a=1;b=1;

#2 a=0;b=0;

end

initial $monitor($time , " a = %b , b = %b ,out carry = %b , outsum = %b " ,a,b,ca,s);

initial #24 $stop;

endmodule

FULL ADDER

module fa(sum,cout,a,b,cin);

input a,b,cin; 

output sum,cout; 

wire s,c1,c2; 

ha ha1(s,c1,a,b), ha2(sum,c2,s,cin); 

or(cout,c2,c1);

endmodule

//test-bench

module tst_fa(); 

reg a,b,cin; 

fa ff(sum,cout,a,b,cin); 

initial

begin

a =0;b=0;cin=0; 

end

always

begin

#2 a=1;b=1;cin=0;#2 a=1;b=0;cin=1;

#2 a=1;b=1;cin=1;#2 a=1;b=0;cin=0;

#2 a=0;b=0;cin=0;#2 a=0;b=1;cin=0;

#2 a=0;b=0;cin=1;#2 a=0;b=1;cin=1;

#2 a=1;b=0;cin=0;#2 a=1;b=1;cin=0;

#2 a=0;b=1;cin=0;#2 a=1;b=1;cin=1;

end

initial $monitor($time ," a = %b, b = %b, cin = %b, 

outsum = %b, outcar = %b ", a,b,cin,sum,cout); 

initial #30 $stop ; 

endmodule

A Byte Comparator

module comp(d,a,b,en);

input en;

input[7:0]a,b;

output d;

wire [7:0]c;

wire dd;

xor g1[7:0](c,b,a);

or(dd,c);

notif1(d,dd,en);

endmodule

module comp_tb;

reg[7:0]a,b;

reg en;

comp gg(d,a,b,en);

initial

begin

a = 8'h00;

b = 8'h00;

en = 1'b0;

end

always

#2 en = 1'b1;

always

begin

 #2 a = a+1'b1;

 #2 b = b+2'd2;

end

initial $monitor($time," en = %b , a = %b ,b = %b ,d = %b ",en,a,b,d);

initial #30 $stop;

endmodule

A-O-I gate program

AOI Gate

module aoi_gate2(o,a);

input [3:0]a; 

output o; 

wire o1,o2; 

and (o1,a[0],a[1]),(o2,a[2],a[3]); 

nor (o,o1,o2); 

endmodule

module aoi_st2; 

reg[3:0] aa; 

aoi_gate2 gg(o,aa); 

initial

 begin 

 aa = 4'b000; 

 #3 aa = 4'b0001;

 #3 aa = 4'b0010;

 #3 aa = 4'b0100;

 #3 aa = 4'b1000;

 #3 aa = 4'b1100;

 #3 aa = 4'b0110; 

 #3 aa = 4'b0011; 

 end 

initial

$monitor( $time , " aa = %b , o = %b " , aa,o); 

initial #24 $stop; 

endmodule

AND Gate Program and its Truth Tabel

module to instantiate the AND gate primitive

module test_and;

reg a1, a2;

wire b;

Initial

Begin

a1 = 0;

 a2 = 0;

 #3 a1 = 1;

 #1 a1 = 0;

 #2 a2 = 1;

 #4 a1 = 1;

 #3 a2 = 0;

 #1 a2 = 1;

end

and g1(b, a1, a2);

initial $monitor ( $time, “a1 = %b, a2 = %b, b = %b”’ a1, a2, b);

initial #100 $finish;

endmodule

DECODER PROGRAMS

Formation of 4-to-16 decoder circuit in terms of smaller decoders: (a) 2-to-4
decoder, (b) 3-to- 8 decoder in terms of two 2-to-4 decoders, and (c) 4-to-16 decoder in 
terms of two 3-to-8 decoders.

2-4 DECODER

module dec2_4 (a,b,en);

output [3:0] a;

input [1:0]b; input en;

wire [1:0]bb;

not(bb[1],b[1]),(bb[0],b[0]);

and(a[0],en, bb[1],bb[0]),(a[1],en, bb[1],b[0]),

(a[2],en, b[1],bb[0]),(a[3],en, b[1],b[0]);

endmodule

//test bench

module tst_dec2_4();

wire [3:0]a;

reg[1:0] b; reg en;

dec2_4 dec(a,b,en);

initial

begin

 {b,en} =3'b000;

#2{b,en} =3'b001;

#2{b,en} =3'b011;

#2{b,en} =3'b101;

#2{b,en} =3'b111;

end

initial

$monitor ($time , "output a = %b, input b = %b ", a, b);

endmodule

3-8 DECODER

module dec3_8(pp,q,enn); 

output[7:0]pp;

input[2:0]q;

input enn; 

wire qq; 

wire[7:0]p;

not(qq,q[2]);

dec2_4 g1(.a(p[3:0]),.b(q[1:0]),.en(qq)); 

dec2_4 g2(.a(p[7:4]),.b(q[1:0]),.en(q[2])); 

and g30(pp[0],p[0],enn); 

and g31(pp[1],p[1],enn); 

and g32(pp[2],p[2],enn); 

and g33(pp[3],p[3],enn); 

and g34(pp[4],p[4],enn); 

and g35(pp[5],p[5],enn); 

and g36(pp[6],p[6],enn); 

and g37(pp[7],p[7],enn); 

endmodule

4-16 DECODER

module dec4_16(m,n);

output[15:0]m;

input[3:0]n;

wire nn; 

//wire en; 

not(nn,n[3]);

dec3_8 g3(.pp(m[7:0]),.q(n[2:0]),.enn(nn)); 

dec3_8 g4(.pp(m[15:8]),.q(n[2:0]),.enn(n[3])); 

endmodule

//test-bench

module dec4_16_stimulus; 

wire[15:0]m;

//wire l,m,n; 

reg[3:0]n;

dec4_16 gg(m,n); 

initial

begin

 n=4'b0000;#2n=4'b0000;#2n=4'b0001; 

#2n=4'b0010;#2n=4'b0011;#2n=4'b0100;

#2n=4'b0101;#2n=4'b0110;#2n=4'b0111;

#2n=4'b1000;#2n=4'b1001;#2n=4'b1010;

#2n=4'b1011;#2n=4'b1100;#2n=4'b1101;

#2n=4'b1110;#2n=4'b1111;#2n=4'b1111;

end

initial $monitor($time," m = %b ,n = %b , gg.g3.qq = %b 

, gg.g4.g1.bb = %b " , m,n,gg.g3.qq,gg.g4.g1.bb);

initial #40 $stop ;

endmodule

BASICS

Logic Synthesis

    //assign z = (a & b) | c;                                       

    // dataflow a assign z = sel ? a : b;

Basic Logic Design with Verilog

Introduction to HDL/ Verilog