HALF ADDER
module ha(s,ca,a,b);input a,b;
output s,ca;
xor(s,a,b);
and(ca,a,b);
endmodule
//test-bench
module tstha();
reg a,b;
wire s,ca;
ha hh(s,ca,a,b);
initial
begin
a=0;b=0;
end
always
begin
#2 a=1;b=0;
#2 a=0;b=1;
#2 a=1;b=1;
#2 a=0;b=0;
end
initial $monitor($time , " a = %b , b = %b ,out carry = %b , outsum = %b " ,a,b,ca,s);
initial #24 $stop;
endmodule
FULL ADDER
input a,b,cin;
output sum,cout;
wire s,c1,c2;
ha ha1(s,c1,a,b), ha2(sum,c2,s,cin);
or(cout,c2,c1);
endmodule
//test-bench
module tst_fa();
reg a,b,cin;
fa ff(sum,cout,a,b,cin);
initial
begin
a =0;b=0;cin=0;
end
always
begin
#2 a=1;b=1;cin=0;#2 a=1;b=0;cin=1;
#2 a=1;b=1;cin=1;#2 a=1;b=0;cin=0;
#2 a=0;b=0;cin=0;#2 a=0;b=1;cin=0;
#2 a=0;b=0;cin=1;#2 a=0;b=1;cin=1;
#2 a=1;b=0;cin=0;#2 a=1;b=1;cin=0;
#2 a=0;b=1;cin=0;#2 a=1;b=1;cin=1;
end
initial $monitor($time ," a = %b, b = %b, cin = %b,
outsum = %b, outcar = %b ", a,b,cin,sum,cout);
initial #30 $stop ;
endmodule
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