input en;
input[7:0]a,b;
output d;
wire [7:0]c;
wire dd;
xor g1[7:0](c,b,a);
or(dd,c);
notif1(d,dd,en);
endmodule
module comp_tb;
reg[7:0]a,b;
reg en;
comp gg(d,a,b,en);
initial
begin
a = 8'h00;
b = 8'h00;
en = 1'b0;
end
always
#2 en = 1'b1;
always
begin
#2 a = a+1'b1;
#2 b = b+2'd2;
end
initial $monitor($time," en = %b , a = %b ,b = %b ,d = %b ",en,a,b,d);
initial #30 $stop;
endmodule
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