AOI Gate
module aoi_gate2(o,a);
input [3:0]a;
output o;
wire o1,o2;
and (o1,a[0],a[1]),(o2,a[2],a[3]);
nor (o,o1,o2);
endmodule
module aoi_st2;
reg[3:0] aa;
aoi_gate2 gg(o,aa);
initial
begin
aa = 4'b000;
#3 aa = 4'b0001;
#3 aa = 4'b0010;
#3 aa = 4'b0100;
#3 aa = 4'b1000;
#3 aa = 4'b1100;
#3 aa = 4'b0110;
#3 aa = 4'b0011;
end
initial
$monitor( $time , " aa = %b , o = %b " , aa,o);
initial #24 $stop;
endmodule
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