Basic Logic Design with Verilog

Introduction to HDL/ Verilog

What is HDL/Verilog 

Why use HDL (Hardware Description Language)?

•  Design abstraction: HDL ←→ layout by human
•  Hardware modeling 
• Reduce cost and time to design hardware

Verilog is one of the most popular HDLs 

• VHDL (another popular HDL) 

Key features of Verilog  

Supports various levels of abstraction 

• Behavior level 
• Register transfer 
• level Gate level 
• Switch level 
• Simulate design functions

Design Description :

Simulation:

The design descriptions are tested for their functionality at every level –
behavioral, data flow, and gate. One has to check here whether all the functions
are carried out as expected and rectify them. All such activities are carried out by
the simulation tool. The tool also has an editor to carry out any corrections to the
source code. Simulation involves testing the design for all its functions, functional
sequences, timing constraints, and specifications. Normally testing and
simulation at all the levels – behavioral to switch level – are carried out by a single
tool; the same is identified as “scope of simulation tool” in Figure 1.5.

LEVELS OF DESIGN DESCRIPTION

Circuit Level

At the circuit level, a switch is the basic element with which digital circuits are

built. Switches can be combined to form inverters and other gates at the next

higher level of abstraction. Verilog has the basic MOS switches built into its

constructs, which can be used to build basic circuits like inverters, basic logic

gates, simple 1-bit dynamic and static memories. They can be used to build up

larger designs to simulate at the circuit level, to design performance critical

circuits. Figure 2.1 shows the circuit of an inverter suitable for description with the

switch level constructs of Verilog.

Gate Level

At the next higher level of abstraction, design is carried out in terms of basic gates. 

All the basic gates are available as ready modules called “Primitives.” Each such 

primitive is defined in terms of its inputs and outputs. Primitives can be 

incorporated into design descriptions directly. Just as full physical hardware can 

be built using gates, the primitives can be used repeatedly and judiciously to build 

larger systems. Figure 2.2 shows an AND gate suitable for description using the 

gate primitive of Verilog. The gate level modeling or structural modeling as it is 

sometimes called is akin to building a digital circuit on a bread board, or on a PCB.

Data Flow

Data flow is the next higher level of abstraction. All possible operations on signals

and variables are represented here in terms of assignments. All logic and algebraic  operations are accommodated. The assignments define the continuous functioning 

of the concerned block. At the data flow level, signals are assigned through the 

data manipulating equations. All such assignments are concurrent in nature. The 

design descriptions are more compact than those at the gate level. 

Lexical Tokens

The characters that are grouped into sets are known as lexical tokens.
Verilog has seven lexical tokens.

1. Keywords
2. Comments
3. White Space Characters
4. Identifiers
5. Strings
6. Numbers
7. Operators