MUX's

4-to-1 mux

module mux4_1(y,i,s);

input [3:0] i;

input [1:0] s;

output y;

wire [1:0] ss;

wire [3:0]yy;

not (ss[0],s[0]),(ss[1],s[1]);

and (yy[0],i[0],ss[0],ss[1]);

and (yy[1],i[1],s[0],ss[1]);

and (yy[2],i[2],ss[0],s[1]);

and (yy[3],i[3],s[0],s[1]);

or (y,yy[3],yy[2],yy[1],yy[0]);

endmodule

//test-bench

module tst_mux4_1();

reg [3:0]i;

reg [1:0] s;

mux4_1 mm(y,i,s);

initial

begin

#2{i,s} = 6'b 0000_00;

#2{i,s} = 6'b 0001_00;

#2{i,s} = 6'b 0010_01;

#2{i,s} = 6'b 0100_10;

#2{i,s} = 6'b 1000_11;

#2{i,s} = 6'b 0001_00;

end

initial

$monitor($time," input s = %b,y = %b" ,s,y);

endmodule

4-to-1 mux module with tri-state

module trimux4_1(o,e,i,s);

input e;

input [1:0]s;

input [3:0]i;

output o;

tri o;

wire y,y1,y2,y3,y4;

wire [1:0]ss;

not(ss[0],s[0]),(ss[1],s[1]);

and g1(y1,ss[0],ss[1],i[0]);

and g2(y2,ss[1],s[0],i[1]);

and g3(y3,ss[0],s[1],i[2]);

and g4(y4,s[1],s[0],i[3]);

or(y,y3,y2,y1,y2);

bufif1 buf2(o,y,e);

endmodule

//TESTBENCH

module tst_trimux4_1();

reg [1:0]s;

reg [3:0]i;

reg e;

wire o;

trimux4_1 tmx4_1(o,e,i,s);

initial

begin

e =0;i =2'b00;

end

always

begin

#6 e=0;s=2'b00;i=4'b0001;

#6 e=1;s=2'b01;i=4'b0010;
#6 e=1;s=2'b10;i=4'b0100;

#6 e=1;s=2'b10;i=4'b1000;

end

initial $monitor($time ," input e = %b , s= %b , i = %b

, output o = %b " ,e,s,i,o);

initial #48 $stop;

endmodule

2-to-1 mux module formed with tri-state
buffers.

module ttrimux2_1(out,e,i,s);

input[1:0]i;

input e;

input s;

output out;

wire o;

bufif0 g1(o,i[0],s);

bufif1 g2(o,i[1],s);

bufif1 g3(out,o,e);

endmodule

//testbench

module ttst_ttrimux2_1();

reg e;

reg [1:0]i;

reg s;

ttrimux2_1 mm(out,e,i,s);

initial

begin

e =0; i = 2'b 00;end

always

begin

#4 e =0;{i,s} = 3'b 01_0;

#4 e =1;{i,s} = 3'b 01_0;

#4 e =1;{i,s} = 3'b 10_1;

#4 e =1;{i,s} = 3'b 00_1;

#4 e =1;{i,s} = 3'b 10_1;

#4 e =1;{i,s} = 3'b 01_0;

#4 e =1;{i,s} = 3'b 00_0;

#4 e =1;{i,s} = 3'b 11_0;

end

initial $monitor($time ," enable e = %b ,

s= %b , input i = %b ,output out = %b ",e ,s,i,out);

initial #48 $stop;

endmodule